Memory systems are known to comprise a plurality of memory cells which are coupled into rows and columns by bit lines and word lines. Each of the memory cells stores digital information, i.e., a logic 1 or a logic 0. To read the digital information from a memory cell, an associated bit line and word line are activated. When activated, the word line couples the bit line to a sensing amplifier, wherein the bit line provides the digital information of the memory cell to a sensing amplifier. As is also known, the sensing amplifier couples the digital information of the memory system to the external components, such as a central processing unit, data processor, etc. As is further known, the memory system may be used in a plurality of applications, such as computers, communication equipment, and any other type of digital circuitry.
To enhance the ability to read data from a memory cell, many memory systems include a pair of bit lines coupled to the memory cell. One of the bit lines functions as the complement of the other wherein both bit lines are provided to a differential sense amplifier. By using the differential bit lines, or complementary bit lines, in conjunction with a differential sense amplifier, data can be more accurately, and more quickly, read from the memory cell. To read the digital information stored in a memory cell accurately, the complementary bit lines must produce a differential voltage in the range of 100 millivolts to 500 millivolts.
There are currently two primary techniques for reading the digital information from a memory cell: a synchronized technique and a self-resetting technique. The synchronized technique utilizes the clock signal to enable the word line and disable precharging of the bit line. At the next clock transition, a sense enable signal is generated which enables the sense amplifier to read the information from the bit lines. While the synchronization technique allows digital information to be read in a pipeline fashion, the technique is not without limitations. For example, as the clock frequency increases, there is less time to establish the necessary differential voltage on the bit lines to insure proper reading of the digital information. Thus, in some applications, the complementary pair of bit lines are not enable long enough to produce a sufficient differential voltage for the sensing amplifier to accurately read the data, which causes errors in the retrieval of the digital information from the memory system. Additionally, the synchronization technique adds delays to the retrieval of data from a memory cell. Delay, or set-up time, is introduced by waiting for transitions in the clock cycle even though the circuitry may be ready to retrieve data well before the next clock cycle transition. As such, a memory system utilizing a synchronization technique may be somewhat time inefficient for nominal processing speeds and may be inaccurate for high processing speeds.
The self-resetting technique begins synchronously with the clock signal when an address signal is received,but thereafter it is asynchronous to the clock. In essence, after the address is decoded, the self-resetting technique is based on the speed of the circuitry and pre-established delay times independent of the clock. After decoding the address, the word line is enabled and a predetermined time later, the sense enable signal is activated. Concurrent to the activation of the word line, precharging of the bit line is disconnected such that data can be read from the bit line when the sense enable signal is activated. The predetermined time is established to ensure that the bit lines will have a sufficient time to charge, or discharge, for proper reading by the sense amplifier. While this technique operates at the speed of the circuitry independent of the clock, thereby overcoming the delay problems of the synchronization technique, it too is not without limitations. For example, if the clock cycle rate is reduced for diagnostic testing of the circuit employing the memory system, or due to process variations, the data may be read too early resulting in an error. Additionally, by having the predetermined time fixed, the self resetting technique does not take advantage of a slower clock to produce a greater bit line margin.
Therefore, a need exists for a method and apparatus that allows data to be retrieved from a memory system in a single clock pipelined without the delays introduced by the synchronization technique and takes advantage of slower clock rates to increase bit line margin.